This three-part report discusses the strengths of FPGAs and how they can be optimally used in software radio systems. It is excerpted from the: handbook of the same name.
Part 1
covered FPGA basics,
Part 2
covered available technologies, and this final part covers product implementations.
Today's programmable logic technology offers significant advantages for designers who need to implement software radio functions. For designers looking to take advantage of an FPGA, the following examples of software radio systems that are available from Pentek show how FPGA technology can be used to quickly develop flexible, powerful designs.
The designs shown below demonstrate that FPGAs are truly an integral part of the latest generation of software radio products. Not only are they being used with traditional digital signal processing algorithms but also in the management of data acquisition, buffering, triggering and timing aspects of high-performance real time systems.
Dual Channel A/D and Wideband Receiver with FPGA
Figure 17 is a block diagram of a dual-channel wideband receiver (model 6235) which is primarily intended for digitizing wideband IF input signals. Each RF input is transformer coupled to the A/D converter to support input signals up to 150 MHz for undersampling applications.
Two AD9432 A/D converters digitize the RF inputs to 12-bit samples. The sampling clock is derived from an internal 100-MHz crystal oscillator, an external front panel reference input or from a low voltage differential signal (LVDS) front panel ribbon cable clock and sync board that can be used to synchronize multiple receivers.
17. Block diagram of a dual-channel wideband receiver.
The A/D digital outputs feed two TI/Graychip GC1012B wideband direct digital controls (DDCs), capable of accepting data at the 100 MHz rate. These chips can be set for decimation values to support output bandwidths from 1.25 to 40 MHz.
Both A/D outputs and both wideband DDC outputs are delivered into a Xilinx Virtex-II Series FPGA. Here, factory default logic allows channel selection, triggering, DDC bypass, and data packing modes. For this design, FPGA densities range from 1 to 3 million gates (XC2V1000 or 3000) and support is available for user-defined custom algorithms.
Dual FPDP Adapter with Virtex-II FPGAs
The Model 6250 dual front panel data port (FPDP) adapter in Figure 18 supports very high-performance custom signal processing functions by incorporating two high-density FPGAs. Two bidirectional FPDP ports transfer 32-bit data at clock rates up 40 MHz. Support for FPDP-II ports allows clock rates as high as 100 MHz (400 MB/sec.)
The FPDP inputs are connected to two Xilinx Virtex-II FPGAs with densities of either 1 or 3 million gates each (XC2V1000 or 3000). The FPGAs are clocked from an on-board 100-MHz crystal oscillator. Factory-default FPGA configuration code includes the FPDP interface and the VIM interface so standard units can be used as fast FPDP adapters.
18. This dual FPDP adapter supports custom signal processing functions by incorporating two high-density FPGAs.
With this design, custom FPGA configuration code can be developed using the optional GateFlow FPGA Design Kit containing the VHDL source for the factory default configuration and provisions for adding user-defined algorithms. Each FPGA is equipped with two 64k x 16 SRAMs for storing data or coefficients, creating a more powerful environment for custom FPGA applications and incorporation of third party IP cores.
Dual Channel Wideband Digital Upconverter and D/A with FPGA
The Model 6228 dual channel wideband digital upconverter in Figure 19 uses two Texas Instruments DAC5686
digital upconverter chips that include an interpolation filter, a local oscillator, a complex mixer and two 16-bit D/A converters.
When operated as a digital upconverter, the maximum clock rate is 320 MHz. This allows digital baseband complex input sampling rates up to 80 MHz and output IF frequencies tunable up to 160 MHz. For the real IF output mode, only one of the 16-bit D/A converters of each DAC5686 is used. For the complex output mode, both D/A converters are used to deliver both I and Q analog signals.
When operated in the D/A only mode, the frequency translation functions are not used. In this mode, the maximum clock frequency for the interpolation filter and D/A converters becomes 500 MHz. With two upconverter chips in the module, four independent data
streams can be delivered to the four 16-bit D/A converters, with optional interpolation for generation of signal bandwidths as high as 200 MHz.
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19. Dual channel wideband digital upconverter.
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