Putting FPGAs to Work in Software Radio Systems, Part 2

Part 1 focuses on the basic elements of a software radio receiver system.
Part 3 focuses on application examples.

The most striking advantage to using an FPGA is its design flexibility, but that does not necessarily mean that designers want to program the entire device. An approach such as Pentek's GateFlow Design Resources can offer multiple ways to design with FPGA products. This type of system allows engineers to choose: their own custom algorithms (GateFlow FPGA Design Kit), off-the-shelf algorithms for high-performance software radio functions (GateFlow IP Core Library), or factory-installed cores.

Adding Custom Algorithms
If you want to add your own algorithms to catalog FPGAs products, look for a design kit that includes VHDL source code for all the standard factory functions. (VHDL is one of the most popular languages used in the FPGA design tools.)

Figure 6 shows a simplified block diagram of a typical software radio module from Pentek showing the FPGA as the large green box and external hardware devices connected to it. The yellow blocks inside the FPGA are VHDL code modules that handle the standard factory functions and interfaces.

The User Block is a VHDL module that sits in the data path with pin definitions for input, output, status, control, and clocks. In the standard product, the User Block is configured as a straight wire between input and output. If the FPGA designer can create an IP core or a custom algorithm inside the User Block so that it conforms to the pin definition, the result will be very low-risk experience in recompiling and installing the custom code. (If the source code is provided, designers can also make changes outside the User Block.)

The GateFlow Design Kit, for example, is intended to be used with the Xilinx ISE Foundation Tool Suite and designers should be trained and familiar with this tool and FPGA design principles, in general. The design kit installs as a complete project file within the ISE environment and includes all the project files that Pentek engineers used to create the standard factory product. These include configuration and definition files, VHDL source, JTAG definition files, and I/O block diagrams. The design kit also includes several utilities, but one important resource is the FPGA Loader Utility.

Normally, the FPGA is loaded from a nonvolatile EEPROM with the standard factory configuration code when the product is powered up. The FPGA Loader Utility allows the processor associated with the FPGA product to reconfigure the FPGA as a software task, effectively overwriting the factory configuration code.

This can be done without turning off power, without disassembling the board or system, and without attaching any special cables or harnesses to the board. In this way, the FPGA can be reconfigured during initialization to install custom operational modes and features. It can also facilitate product upgrades and enhancements to dramatically extend product longevity.

The Loader Utility is especially useful as a runtime resource. The user can select a new mode of operation and cause a new FPGA configuration upload, to implement that mode as part of the runtime executable code.

Designing for speed with off-the-shelf algorithms
Dozens of FFT IP cores are available but Figure 7 shows two examples of 1k and 4k complex FFTs that have been optimized for speed. Calculation time is proportional to clock speed and the maximum clock depends on the speed grade of the FPGA devices.

For these cores, the -6 device can be operated up to 140 MHz. But at a reference clock frequency of 100 MHz, the core 404 executes a 4k complex FFT in just over 10 μsec. How does that compare with a general purpose DSP or RISC processor? In fact, a 500 MHz G4 PowerPC takes ten times longer and a 300 MHz TI C6203 takes 20 times longer. The message here is that if you need to do a fast FFT, strongly consider doing it in an FPGA.

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