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PIN diodes are ideal for transmit-receive (TR) switches because of a favorable blend of cost, size, and switching speed. Although the PIN diode in the transmit (Tx) arm can be connected as either series or shunt switching element, the former is potentially more linear [1]. During transmitting, a series PIN switch is biased ON, whereas a shunt PIN is turned OFF. In the shunt connection, the large RF signal voltage modulates the unbiased PIN diode's junction capacitance due to the varactor effect and this generates significantly more distortion. As a result, series PIN switches are preferred in applications that emphasize linearity.
General RF characteristics of PIN diode
The PIN diode consists of a layer of intrinsic (high resistivity) material of finite area (A) and thickness (W) which is contained between highly doped p and n type material. When the diode is forward biased, charge is injected into the intrinsic or "I" region. This charge consists of holes and electrons which have a finite lifetime before recombination. The density of charge in the intrinsic region and its geometry determines the conductance of the device.
The thickness of the intrinsic region determines the minority carrier lifetime τ. The cutoff frequency (fc) is related to τ by:
The PIN diode's low frequency limit of useful application is governed by these parameters. Below 10fc, the PIN diode behaves like a conventional PN junction; rectifying the applied RF signal and creating copious amount of distortion. However, above 10fc, the PIN diode functions like a current controlled resistor; this is where signal can pass through the switch relatively undistorted. The PIN diode described here has τof greater than 200ns and is suitable for use above 10MHz.
The junction resistance, Rs, can be changed from high to low by the application of a forward bias current. The series connected switch has an insertion loss, A, corresponding to [2]:
The PIN diode switch is more robust and linear than its FET counterpart. The former is able to tolerate switching in the presence of RF power which is also known as "hot-switching," whereas, the FET switch can be damaged by the transition through a resistance region where significant power is dissipated [3]. Additionally, the PIN diode can handle larger power in the non-conducting state as it has a highest breakdown voltage (VBR) among competing switch technologies. Above 5 to 30MHz, the silicon PIN switch generates less distortion and consequently achieves a higher third order intercept point (IP3) than FET-based switches [4,5]. Additionally, within the power dissipation limit, the PIN diode's linearity may be raised if so desired by increasing the bias current [6].
1. Table 1 Breakdown voltages for various semiconductor switch technologies.
Product design
Microwave PIN diodes have small junction area to minimize parasitics. When a typical SOT-packaged PIN diode is used as a series switch, it can handle about 30 to 37dBm of power. To achieve the targeted +40 dBm power handling, one technique is to combine smaller diodes to form a larger one. This technique requires the diode dices to be well matched to prevent one die from hogging more current than the other.
The traditional method of hand-matching diodes from unrelated wafers (e.g. comparing the forward voltage, Vf, at 1mA of bias current) generally yields inferior results as the DC parameters may have little relation to the RF characteristics. A more production-friendly method involves cutting a diode wafer into arrays of dices. As each array consists of dices from adjacent site, the diodes are well matched in RF characteristic [7]. A QFN package measuring 2 mm on each side was chosen for the following reasons: industry standard footprint, low cost plastic and lead-frame materials, and low thermal resistance (θjc = 45 C/W) due to large center lead. Among competing parts, this design has both the smallest footprint and the lowest thermal resistance for a low cost plastic package. Its thermal resistance only loses out to the more expensive ceramic-packaged parts.
Parameter extraction and model fitting
The model parameters are derived by curve-fitting to the measured insertion loss and isolation in the series switch configuration. The diode model is based the single die version demonstrated by Piper [8] and the initial model parameters taken from published data of this PIN family[9]. The two package dependent parameters, bond-wire inductance (Lpkg) and pad-to-pad capacitance (Cpkg) were varied to fit the measurement.
1. Simulation circuit of series switch evaluation board.
The main contributor of insertion loss at low frequencies is the intrinsic layer's finite conductance at rated bias current If. However, as the frequency goes up, the PIN's equivalent series inductance (Lpkg), consisting of the bond-wire and lead parasitic, becomes increasingly dominant in influencing the switch's loss. For a bond-wire of the length l and diameter d (in microns), the inductance (in nH) is:
where δ is skin depth [10]. The package design minimizes Lpkg by using a multiplicity of bond-wires and leads for the anode and cathode connections.
2 Measured and simulated series switch insertion loss at 50mA bias.
Under zero-bias condition, the PIN diode behaves like a fixed value capacitor at frequencies above the dielectric relaxation frequency (≈500 MHz for this device) given by:
where ρ is the resistivity of the I-region and the dielectric constant of silicon [2]. Since the PIN junction capacitance is proportionate to the junction area A,
its value will be adversely large in a compound PIN device that was dimensioned for handling large power. On a smaller magnitude is the parasitic capacitance formed of dielectric material (i.e. mold compound) between the opposing lead-frame pads inside the package [11]. The combined package (Cpkg) and junction (Cj) capacitances are important considerations in the PIN switch design as they allow the RF signal to leak around the high junction resistance in the unbiased state. This leakage degrades the isolation of the series switch during the "turned off" mode, causing it to drop at a rate 6dB per octave. Evaluation of the device at zero bias showed that at 4GHz and above, it is totally bereft of any isolation. Fortunately, there is a circuit trick for recovering the lost isolation by resonating out the parasitic capacitances with an external inductor [12] and this is shown in the application example.
3 Measured and simulated series switch isolation at zero bias.
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